1. Field of the Invention
The present invention relates to a sense amplifier circuit for detecting and amplifying data of a selected memory cell in a semiconductor memory device, and more particularly, it relates to an improvement to a sense amplifier circuit which generates a sense current on an internal data line in accordance with data of a selected memory cell.
2. Description of the Background Art
In recent years, semiconductor memory devices are increasingly improved in operating speed. For example, a static random access memory (SRAM) has an access time of not more than 10 ns (nanoseconds). In relation to such SRAM, various improvements are proposed in order to attain large storage capacity, high-speed operability and low power consumption.
FIG. 14 shows an overall structure of a conventional SRAM. Referring to FIG. 14, the SRAM includes a memory cell array 700 having static memory cells which are arranged in a matrix of rows and columns, an X address buffer 702 which receives an X address for generating an internal X address, an X decoder 704 which decodes the internal X address received from the X address buffer 702 for selecting a row (word line) in the memory cell array 700, a Y address buffer 706 which receives a Y address for generating an internal Y address, a Y decoder 708 which decodes the internal Y address and generates a column selection signal for selecting a prescribed number of columns (bit line pairs) in the memory cell array 700, and a Y select gate 710 which connects a corresponding column to an internal data line in response to the column selection signal.
The number of the columns specified by the Y decoder 708 is varied with the bit organization of the SRAM. A single column is selected when data are inputted/outputted in a unit of one bit, while a plurality of columns are selected when data are inputted/outputted in a unit of a plurality of bits. When the memory cell array 700 is divided into blocks, the Y decoder 708 also generates a signal for specifying a block.
The SRAM further includes a first sense amplifier circuit 712 which detects and amplifies data on the column(s) selected by the Y select gate 710, and a second sense amplifier circuit 714 which further amplifies the data amplified by the first sense amplifier circuit 712. The first and second amplifiers 712 and 714 are so provided as to reduce a signal swing in the internal data line, thereby increasing the speed of the sensing operation.
The SRAM further includes an output buffer 716 which generates external read data from the data amplified by the second sense amplifier circuit 714, an input buffer 718 which receives externally supplied write data and generates internal write data in data writing, and a write driver 720 which transmits the internal write data received from the input buffer 718 onto the column(s) selected by the Y select gate 710. Referring to FIG. 14, symbol DQ denotes the external write data and the external read data, which are inputted/outputted through a common pin terminal. This pin terminal may be replaced by separate pin terminals.
As is well known in the art, a memory cell which is located on an intersection of a row (word line) and a column (bit line pair) specified by X and Y addresses is selected in data writing or reading of an SRAM. Data is written in or read from the selected memory cell.
FIG. 15 shows the structure of a principal part of a conventional semiconductor memory device. The semiconductor memory device shown in FIG. 15 is an SRAM, which is disclosed in ISSCC Digest of Technical Papers, February 1992, pp. 210 to 211 by Kato et al., for example. This figure illustrates a principal part of the circuit structure of the SRAM which is shown in the above literature in a simplified manner. The SRAM shown in FIG. 15 comprises NPN bipolar transistors and complementary field effect transistors (CMOS transistors) as components. Referring to FIG. 15, parts corresponding to the elements shown in FIG. 14 are denoted by the like reference numerals employed in relation to FIG. 14, for the purpose of reference.
Memory cell array 700 includes static type memory cells 61, which are arranged in rows and columns. FIG. 15 typically shows only one of such memory cells 61. Each static type memory cell 61 includes N-channel MOS transistors 613 and 614 having gates and drains cross-connected and high-resistance elements 611 and 612 for pulling up the drains (nodes NL and NR) of the transistors 613 and 614 to a first source potential VDD. The high-resistance element 611 and the N-channel MOS transistor (driver transistor) 613 form an inverter circuit, while the high-resistance element 612 and the N-channel MOS transistor (driver transistor) 614 form another inverter circuit. These inverter circuits are cross-connected with each other.
The static type memory cell 61 further includes access transistors 615 and 616, which are formed by N-channel transistors respectively. The access transistors 615 and 616 connect the nodes NL and NR to bit lines 63 and 64 in response to a signal potential on a word line 62, respectively. The bit lines 63 and 64, which are paired with each other, receive complementary signals. These bit lines 63 and 64 are provided with load elements 65 and 66 for supplying currents to the bit lines 63 and 64. The load element 65 is formed by a P-channel MOS transistor which is resistively connected between the source potential VDD and the bit line 63. The other load element 66 includes a P-channel MOS transistor serving as a resistance which is connected between the source potential VDD and the bit line 64. These load elements 65 and 66 may be formed by high-resistance elements of polysilicon or the like.
First sense amplifier circuit 712 includes a sense amplifier 60 which is provided for the bit lines 63 and 64. Such sense amplifier 60 is provided for each respective bit line pair. FIG. 15 shows a first sense amplifier 6G which is provided for another bit line pair BL and /BL.
The first sense amplifier 60 includes NPN bipolar transistors 69 and 6A having emitters connected in common, and an N-channel MOS transistor 6B which couples the emitters of the bipolar transistors 69 and 6A to a second source potential (ground potential) in response to a bit line selection signal YS. The transistors 69, 6A and 6B form a differential amplifier of an emitter coupled logic type.
The first sense amplifier 60 further includes first and second level shifters for preventing the transistors 69 and 6A from being saturated. The first level shifter includes an NPN bipolar transistor 67A having a base which is coupled to the bit line 63, an emitter which is connected to a base of the transistor 69 and a collector which is connected to the source potential VDD, and an N-channel MOS transistor 68A which couples the base of the transistor 69 to the ground potential in response to the bit line selection signal YS. The other level shifter includes an NPN bipolar transistor 67B having a base which is connected to the bit line 64, a collector which is connected to the source potential VDD and an emitter which is connected to a base of the bipolar transistor 6A, and an N-channel MOS transistor 68A which couples the base of the bipolar transistor 6A to the ground potential in response to the bit line selection signal YS. The transistors 67A and 67B operate in an emitter follower mode, to shift in level the potentials of the bit lines 63 and 64 and transmit the same to the bases of the transistors 69 and 6A. The transistors 68A and 68B form a Y select gate, while the transistor 6B forms a Y select gate and a sense amplifier driving circuit.
When a bipolar transistor is saturated, both of base-collector and base-emitter junctions are forward-biased in general. Since a forward-biased junction diode has high diffusion capacitance, a collector current is not reduced until the collector-base junction is biased in the reverse direction. When the bipolar transistor is driven in a saturation region, its switching speed is slowed. A level shifter is provided in order to drive the bipolar transistor in a non-saturated state for attaining a high speed operation. An output of the first sense amplifier 60 is transmitted to data lines 6C and 6D.
The second sense amplifier circuit 714 includes a second sense amplifier 6E which generates a voltage signal in accordance with currents on the data lines 6C and 6D. The second sense amplifier 6E includes clamp diodes 6El and 6E2 for clamping the data lines 6C and 6D at prescribed potentials, current sources 6E9 and 6EA for supplying constant steady-state currents to the clamp diodes 6El and 6E2 respectively, NPN bipolar transistors 6E5 and 6E6 forming an emitter coupled logic for differentially amplifying potentials on the data lines 6C and 6D, a current source 6EB for sinking currents from the transistors 6E5 and 6E6, resistance elements 6E3 and 6E4 for generating voltage signals in accordance with collector currents of the transistors 6E5 and 6E6, and NPN bipolar transistors 6E7 and 6E8 for driving output signal lines 6EF and 6EG in accordance with the voltage signals generated by the resistance elements 6E4 and 6E3 respectively. Emitters of the transistors 6E7 and 6E8 are connected with current sources 6EC and 6ED respectively. The current sources 6E9 and 6EA supply the same constant currents.
An output of the second sense amplifier 6E is transmitted to an output circuit 6F, which may be included in the output buffer 716, or may be a preamplifier provided in a front stage of the output buffer 716. The operation of the sense amplifier circuit, i.e., an operation for reading data from the memory cell 61 is now described.
In order to select the memory cell 61, the word line 62 which is connected with the memory cell 61 and the bit line selection signal YS for selecting the bit line pair which is connected with the memory cell 61 are brought into to high potential levels. For convenience of illustration, it is assumed here that the memory cell 61 is maintained in such a state that the node NL is at a high potential (equal to the source potential VDD) and the other node NR is at a low potential (equal to the ground potential). It is also assumed that the bit lines 63 and 64 are precharged at the high potential in advance of data reading.
When the potential of the word line 62 goes high, the access transistors 615 and 616 enter ON states. The potential of the node NR is at a low level and a current flows into the node NR from the bit line 64 through the transistor 616. This current is supplied from the source potential VDD through the load element 66 which is provided on the bit line 64. The current flows through the bit line 64 and the potential of this bit line 64 is reduced by resistance of the load element 66.
The node NL is connected to the bit line 63 through the transistor 615. The potential of the node NL is at a high level. Since the bit line 63 and the node NL are at the same potential, no current flows to the node NL through the transistor 615. Namely, no current flows to the load element 65 provided on this bit line 63, and hence the potential of the bit line 63 remains at the precharged high level. The potentials of the bit lines 63 and 64 are supplied to the bases of the transistors 67A and 67B, level-shifted by base-to-emitter forward voltages (VBE) of the transistors 67A and 67B and supplied to the bases of the bipolar transistors 69 and 6A (when the transistors 68A and 68B enter ON states).
When the potential of the bit line selection signal YS goes high, the transistors 68A, 68B and 6B enter conducting states. The bipolar transistors 67A and 67B, which operate in an emitter follower mode, have functions of clamping the emitter potentials. Since the potential of the bit line 63 is at a high level and that of the bit line 64 is at a low level, the bipolar transistor 69 enters an ON state and the bipolar transistor 6A enters an OFF state. The value of a current flowing in the bipolar transistor 69 is decided by current drivability of the transistor 6B.
in the second sense amplifier 6E, the current sources 6E9 and 6EA are set to supply equal amounts of currents. When no currents flow in the data lines 6C and 6D, the bipolar transistors 6E5 and 6E6 have equal base potentials. In data reading, a current flows in one of the data lines 6C and 6D. In this case, the bipolar transistor 69 is in an ON state and a current flows from the data line 6C through the bipolar transistor 69 and the MOS transistor 6B. The data line 6C is supplied with a current from the source potential VDD through the diode 6El. Therefore, the value of the current flowing through the diode 6El exceeds that of the current flowing through the diode 6E2. Thus, the base potential of the bipolar transistor 6E5 becomes slightly lower than that of the bipolar transistor 6E6, whereby the bipolar transistor 6E5 enters a nonconducting state and the bipolar transistor 6E6 enters a conducting state.
Such conduction of the bipolar transistor 6E6 feeds a current to the resistance element 6E4 and reduces the base potential of the bipolar transistor 6E7. The base potential of the bipolar transistor 6E8 is at a high level since no current flows through the resistance element 6E3. The bipolar transistor 6E7 and 6E8 operate in an emitter follower mode in accordance with the base potential, and drive the output signal lines 6EF and 6EG. The potential of the output node 6EF becomes lower than that of the output node 6EG. The signal potentials of the output nodes 6EF and 6EG are further amplified by the output circuit 6F, whereby read data are generated.
In the conventional sense amplifier circuit shown in FIG. 15, as hereinabove described, the potential difference between the bit lines 63 and 64 is converted to current difference by the first sense amplifier 60, and this current difference is again converted to the potential difference by the second sense amplifier 6E.
The data lines 6C and 6D are generally connected with a number of first sense amplifiers 60 corresponding to the bit line pairs. Since a number of memory cells are connected to a single row, interconnection lengths of the data lines 6C and 6D are increased. Thus, the data lines 6C and 6D have large parasitic capacitances. Since potential changes on the data lines 6C and 6D in data reading accompany charge/discharge of the large parasitic capacitances, time delay is so increased that the sensing operation cannot be performed at a high speed. In order to minimize the potential changes on the data lines 6C and 6D, the diodes 6E1 and 6E2 clamp the potentials of the data lines 6C and 6D for transmitting the signals to the second sense amplifier 6E in current modes.
The conventional sense amplifier circuit shown in FIG. 15 has the following problems:
(1) As hereinabove described, it is necessary to minimize the potential changes in the data lines 6C and 6D since the signal transmission time to the second sense amplifier 6E is increased with the potential changes. In order to reduce the potential changes, the diodes 6E1 and 6E2 clamp the potentials of the data lines 6C and 6D. When a current IF flows through a diode, potential difference VF developed between an anode and a cathode of this diode is generally expressed as follows: EQU VF=VT.multidot.ln (IF/A)
where VT represents a coefficient changing in accordance with a temperature which is generally expressed as k.multidot.T/q. This coefficient is about 26 mV at the room temperature. Further, k represents the Boltzmann's constant, q represents the amount of charges of an electron, T represents an absolute temperature, and A represents a constant.
It is assumed here that the currents supplied by the current sources 6E9 and 6EA are set at 0.1 mA and the current supplied by the transistor 6B, i.e., a sense current, is set at 0.5 mA. Assuming that a current of 0.1 mA flows through a diode and this diode has potential difference VF of 0.8 mV, potential difference of about 0.85 V is developed in the diode upon flowing of a sense current since a current of 0.6 mA flows through the diode. Thus, a potential swing at the data line 6C (or 6D) can be suppressed to 0.85-0.8 (V), i.e., 50 mV.
This potential difference is amplified by the bipolar transistors 6E5 and 6E6 provided in the second sense amplifier 6E. As the potential difference between the data lines 6C and 6D is reduced, it is difficult to completely switch conduction/nonconduction of the emitter-coupled bipolar transistors 6E5 and 6E6. Thus, the output swing of the second sense amplifier 6E (potential difference between the output nodes 6EF and 6EG) is reduced and the time required for amplifying the potentials in the second sense amplifier 6E is increased, since both of the bipolar transistors 6E5 and 6E6 feed currents. Namely, conditions required for attaining high speed operation of the first and second sense amplifiers 60 and 6E collide with each other.
(2) The output potential swing of the second sense amplifier 6E cannot exceeds 0.8 V, in order to prevent the bipolar transistors 6E5 and 6E6 from being saturated. More specifically, the swing of the output potential of the second sense amplifier 6E is equal to those of the collector potentials of the bipolar transistors 6E5 and 6E6. Assuming that a potential drop at the diode 6E2 is 0.8 V, the base potential of the bipolar transistor 6E6 is VDD-0.8 V. If the second sense amplifier 6E has an output potential swing of 1.0 V, for example, the collector potential of the bipolar transistor 6E6 is VDD-1.0 V, and this bipolar transistor 6E6 operates in a saturated state since its base-collector junction is biased in the forward direction. In order to prevent this state, the output potential swing of the second sense amplifier 6E cannot exceed 0.8 V.
This potential swing of 0.8 V may cause no serious problem if an interface is an ECL (emitter coupled logic), since a high potential level is -0.9 V and a low potential level is -1.7 V in such an emitter coupled logic with a potential swing of 0.8 V. When the interface is a TTL (transistor-transistor logic) having a high potential VIH of an input signal of 2.0 V and a low potential VIL of 0.8 V or a CMOS having a high potential of a source potential level and a low potential of the ground potential level, however, the potential swing is 1.2 V or 5 V (when an operating source potential is 5 V), and no interface can be attained in this case. In order to interface with TTL or CMOS circuitry, the output circuit 6F must be provided with a level converter for further voltage amplification, and hence the delay time is increased in the output circuit 6F.
(3) The second sense amplifier 6E requires five current sources 6E9, 6EA, 6EB, 6EC and 6ED. When this semiconductor memory device inputs and outputs data in a unit of a plurality of bits, it is necessary to provide the second sense amplifiers 6E in a number equal to that of the bits forming the input/output unit, and hence the current consumption is remarkably increased. When the memory device is applied to a by 32-bit organization memory containing type processor, 32 second sense amplifiers 6E are required to require 160 (5.times.32) current sources, resulting in a large current consumption.